Sound processing optimization using fpga

FPGA technology has gained a lot of attention in real time processing community as the demand for increasingly complex real time signal processing rises. This is due to appealing performance metrics that are available with FPGA architectures. However, the development complexity significantly increases time and required experience measures, thus reduces the popularity of such implementations for broader consumption. In order to cope with this problem, high level synthesis (HLS) concept was introduced, but the effectiveness of such tools for sound processing tasks optimization is not clear. In this paper popular HLS tools - ROCCC, Vivado HLS and LegUp were compared in order to assess their capabilities. During the experiment, LegUp's effectiveness was tested with one of the sound processing tasks - fast Fourier transform calculation. Functionality was implemented in C, synthesized (with and without loop optimizations) and compared with the performance and resource consumption of manual implementation of such algorithm written in Verilog. Performance measures (Fmax, cycle count, latency), resource measures (logic elements, memory bits, registers), development time and code size were taken into consideration. It was found that manual Verilog implementation tend to have better performance scores, however it consumes far more FPGA resources than synthesized with minimal optimizations version of the algorithm. Synthesized results were also better from the code size (up to 3 times less) and development time (up to 6 times less) perspectives