Setmap: a soft error tolerant mapping algorithm for FPGA designs with low power

Field programmable gate arrays (FPGAs) are widely used in VLSI applications due to their flexibility to implement logical functions, fast total turn-around time, and low non-recurring engineering cost. The most popular FPGAs in the market are SRAM-based FPGAs. However, as process technologies advance to nanometer-scale regimes, the issue of reliability of devices becomes critical. Soft errors are increasingly becoming a reliability concern because of the shrinking process dimensions. In this thesis, we study the technology mapping problem for FPGA circuits to reduce the occurrence of soft errors under the chip performance constraint and power reduction. Compared to two power-optimization mapping algorithms, SVmap and Emap, respectively, we reduce the single event upset (SEU) rate by 30.5% with a 3.7% power overhead penalty and 50.1% with a 4.7% power overhead penalty using six-input LUTs. When multi-event upset (MEU) occurs, our work reduces the soft error rate by 33% and 31.5% for double bit flips and triple bit flips, respectively, compared to SVmap, and by 52.9% and 50.3% for double bit flips and triple bit flips, respectively, compared to Emap