High Level Synthesis of Globally Asynchronous Locally Synchronous Circuits

International audienceThis paper presents an approach for the design of Globally Asynchronous Locally Synchronous (GALS) circuits. The mixed style using asynchronous and synchronous circuits amalgamates the both styles best features. A language for high level specification of circuits is described. Then, the synthesis method that maps the algorithmic level specification in a net of GALS circuits is given. The asynchronous part is highlighted and avoidance of metastability is described. Finally, the link to existing CAD tools is given via VHDL