Using VHDL for Link to Synthesis Tools

Belhadj, Mohammed

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Publication date

June 1994

DOI

10.1109/ATW.1994.747844

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Abstract

International audienceThis paper presents the work done to use industry and academic synthesis tools for the hardware-software codesign of reactive systems. It emphasizes the hardware synthesis and design part by linking SIGNAL and VHDL. The SIGNAL language is used for system specification and VHDL for the link to synthesis tools. To permit a maximum of flexibility, different strategies for linking are described

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Using VHDL for Link to Synthesis Tools

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Using VHDL for Link to Synthesis Tools

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