Drifting-dipole noise model of nanometer MOSFETs for radio frequency integrated circuit design

Recent advances in nanometer CMOS scaling technology have made transistors capable of operating at hundreds of gigahertz, and opened a new era of high performance, low cost system-on-chip (SOC) designs for multi-gigabit-per-second wireless communication. However, such achievements also bring new challenges, particularly in modeling the physical behaviors of these super-scaled devices. Among these issues, it is found that the thermal-noise based formulation, such as the one in the widely accepted BSIM model, starts to deviate from the measured noise parameters of 120-nm CMOS devices. Therefore a new high-frequency noise model is required to allow first-pass radio frequency integrated circuit (RFIC) designs using state-of-the-art CMOS technologies. As the MOSFET is scaled down, the lateral field across the device channel becomes comparable to, or even exceeds, the vertical field. The device can no longer be considered as operating under equilibrium condition, and the thermal noise theory is no longer applicable to predicting its performance. This work describes a new noise formulation that takes into account high-field effects by using the concept of unrelaxable drifting dipoles. The proposed noise model is verified for single devices as well as for integrated circuits. Excellent fitting results are achieved for the measured noise parameters of single 120-nm MOSFETs. For circuit validation, two high-performance low-noise amplifiers (LNA) have been demonstrated. The 3.1???10.6 GHz Ultra Wideband LNA shows very low noise figures NF of 3.5 to 4.3 dB as well as superior input-referred third-order interception points IIP3 of 3.5 to 5.2 dBm across the design bandwidth. The other circuit, a 24-GHz LNA, achieves a gain of 19 dB, the highest gain published to date at this frequency band, while maintaining a comparative noise figure NF of 3.8 dB