Timing Analysis and Behavioral Synthesis with Process Variation

The move to deep submicron processes has brought about new problems that designers must contend with in order to obtain functional circuits. Process variation has been recognized as one of the leading issues that must be dealt with in deep submicron processes. The problems experienced with deep submicron processes have ushered in a new era of statistical design, in which process parameters are no longer considered to be deterministic but are modeled as probability distributions. In order to support statistical design, new algorithms and methods are needed. One of the chief problems with process variation is the need for accurate timing analysis in which process parameters such as gate length and oxide thickness are now modeled as probability density functions (pdf) instead of deterministic quantities. Statistical static timing analysis (SSTA) has emerged to fi ll that void. Much work has been performed in the realm of SSTA; however, the majority of it has focused on improving the main SSTA algorithm. The first piece of work that will be presented in this thesis extends SSTA to be able to handle complicated timing constraints such as multi-clock domain circuits, false paths, and multi-cycle paths. The second piece of work extends the behavioral synthesis task of binding to be variation-aware through our algorithm FastYield. FastYield off ers several contributions to the field of statistical design. First, it presents the unit correlation model, a model that can be used to model correlation at the functional unit level. Second, it offers a bipartite matching formulation for variation-aware binding in high-level synthesis. Last, it presents a statistical timing-driven floorplanner that is used to obtain correlation and interconnect information for more accurate timing analysis