The proliferation of multi-core, accelerator-enabled embedded systems has introduced new opportunities to consolidate real-time systems of increasing complexity. But the road to build confidence on the temporal behavior of co-running applications has presented formidable challenges. Most prominently, the main memory subsystem represents a performance bottleneck for both CPUs and accelerators. And industry-viable frameworks for full-system main memory management and performance analysis are past due. In this paper, we propose our Envelope-aWare Predictive model, or E-WarP for short. E-WarP is a methodology and technological framework to: (1) analyze the memory demand of applications following a profile-driven approach; (2) make realistic pre...
The world needs special-purpose accelerators to meet future constraints on computation and power con...
Parallelism is ubiquitous in modern computer architectures. Heterogeneity of CPU cores and deep memo...
The reduced space, weight and power(SWaP) characteristics of multi-core systems has motivated the re...
Timing analysis of safety-critical real-time embedded systems should be free of both optimistic and ...
International audienceMemory interferences may introduce important slowdowns in applications running...
Disaggregated memory has recently been proposed as a way to allow flexible and fine-grained allocati...
There is an increasing interest among real-time systems architects for multi- and many-core accelera...
Application performance often depends on achieved memory bandwidth. Achieved memory bandwidth varies...
The multicore era has initiated a move to ubiquitous parallelization of software. In the process, co...
International audienceThis work presents a realistic performance model to execute scientific workflo...
Memory contention is one of the largest sources of inter-core interference in statically partitioned...
This paper proposes RPPM which, based on a microarchitecture-independent profile of a multithreaded ...
As the speed gap widens between CPU and memory, memory hierarchy performance has become the bottlene...
Consolidation of multiple applications with diverse and changing resource requirements is common in ...
The world needs special-purpose accelerators to meet future constraints on computation and power con...
Parallelism is ubiquitous in modern computer architectures. Heterogeneity of CPU cores and deep memo...
The reduced space, weight and power(SWaP) characteristics of multi-core systems has motivated the re...
Timing analysis of safety-critical real-time embedded systems should be free of both optimistic and ...
International audienceMemory interferences may introduce important slowdowns in applications running...
Disaggregated memory has recently been proposed as a way to allow flexible and fine-grained allocati...
There is an increasing interest among real-time systems architects for multi- and many-core accelera...
Application performance often depends on achieved memory bandwidth. Achieved memory bandwidth varies...
The multicore era has initiated a move to ubiquitous parallelization of software. In the process, co...
International audienceThis work presents a realistic performance model to execute scientific workflo...
Memory contention is one of the largest sources of inter-core interference in statically partitioned...
This paper proposes RPPM which, based on a microarchitecture-independent profile of a multithreaded ...
As the speed gap widens between CPU and memory, memory hierarchy performance has become the bottlene...
Consolidation of multiple applications with diverse and changing resource requirements is common in ...
The world needs special-purpose accelerators to meet future constraints on computation and power con...
Parallelism is ubiquitous in modern computer architectures. Heterogeneity of CPU cores and deep memo...
The reduced space, weight and power(SWaP) characteristics of multi-core systems has motivated the re...