Fast Power Estimation at the architectural Level

International audienceWith the emergence of embedded processing systems, the power dissipation of very large scale integrated circuits is becoming a critical concern. Therefore power requirements are driving a new breed of computer-aided design tools. This paper addresses the problem of modeling power dissipation at a high level of abstraction. A modeling approach is presented that captures the dependence of the circuit modules power dissipation on theirs activities. We also introduce our RT level estimation tool, PowerCheck,partoftheBSS framework Breizh Synthesis System, http://archi.enssat.fr. PowerCheck takes place after the RTsynthesis, then it by the architecture and its use. The major interest of our approachisthatwe takeinto account the signal properties in our power dissipation estimates of complete architecture