An Empirical High Level Performance Model For FutureMany-cores

International audienceEstimating the potential performance of parallel applicationson the yet-to-be-designed future many cores is veryspeculative. The simple models proposed by Amdahl's law(xed input problem size) or Gustafson's law (xed numberof cores) do not completely capture the scaling behaviourof a multi-threaded (MT) application leading to over estimationof performance in the many-core era. On the otherhand, modeling many-core by simulation is too slow to studythe applications performance.In this paper, we propose a more rened but still tractable,high level empirical performance model for multi-threadedapplications, the Serial/Parallel Scaling (SPS)Model to studythe scalability and performance of application in many-coreera. SPS model learns the application behavior on a givenarchitecture and provides realistic estimates of the performancein future many-cores. Considering both input problemsize and the number of cores in modeling, SPS model canhelp in making high level decisions on the design choice of futuremany-core applications and architecture. We validatethe model on the Many-Integrated Cores (MIC) xeon-phiwith 240 logical cores