Timing correction technique for fast and accurate state-based performance models

International audienceEarly performance evaluation of embedded systemsextensively uses discrete-event simulation of high levelarchitecture models. Due to increasing complexity of systemarchitectures, simulation speed needs to be improved to guaranteeevaluation of candidate architectures in acceptable time. In thispaper, we introduce a timing correction technique that allowsthe number of processes managed by the simulation kernelto be reduced. The presented technique uses knowledge aboutapplication and platform to preserve accurate simulation resultsin case of contention at shared resources. We have implementedthis simulation technique into an industrial modeling framework.Our experiments show that a simulation speed-up by a factorof 7 can be achieved with no loss of accuracy. The proposedapproach has thus potential to improve the evaluation process ofarchitectures