RSA processor design with vedic multiplier for nodes in wireless sensor networks

Due to the resource constraints of Wireless Sensor Nodes the fast multipliers are essential for data processing. In this paper, we propose the RSA processor using Vedic multiplication technique that achieves considerable speed and with reduced area utilization. To multiply two prime numbers we have implemented Nikhilam and Urdva Triyagbagam multipliers. The results of our Hardware implementation on Xilinx Spartan III FPGA can be used for the construction of security architecture in WSN. The delay and area tradeoff leads to the selection of multiplier for RSA processor. The comparative analysis of the two different methodologies is analyzed in terms of speed and area. Urdva Triyagbagam gives good improvement in delay and device utilization compared to Nikhilam Multiplier