Thesis (M.S.)--University of Kansas, Electrical Engineering & Computer Science, 2007.This thesis presents the design of a Symmetric Multiprocessor (SMP) hybridthreads (hthreads) system that allows multiple threads to execute in parallel across multiple processors controlled by a single hardware scheduler. This approach increases the performance of software at a minimal cost to hardware. The issues that must be addressed for extending a uniprocessor kernel include system initialization, processor identification, context switching and concurrency control. As a proof of concept this thesis shows how hthreads, an existing hardware/software co-designed kernel can be extended to control multiple processors from a single, centralized hardware sche...
Existing multiprocessor synchronization mechanisms are relatively heavyweight, due in part to the le...
In this dissertation, we address the problem of performance efficient multithreading execution on he...
A simultaneous multithreading (SMT) processor can issue instructions from several threads every cycl...
In this paper we first outline and discuss the issues of currently accepted computational models for...
In this paper, we present hthreads, a unifying pro-gramming model for specifying application threads...
Hybrid chips containing both CPU's and FPGA components promise the potential of providing a uni...
Abstract 1 This paper discusses the preliminary performance study of hybrid multithreaded execution ...
This thesis proposes, develops, and evaluates hardware and software mechanisms that enhance the effi...
Recently emerging hybrid chips containing both CPU's and FPGA components have the potential to ...
Abstract—This paper introduces hthreads, a unifying program-ming model for specifying application th...
Multithreaded processors are now common in the industry as they offer high performance at a low cost...
Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous ...
This paper evaluates new techniques to improve performance and efficiency of Chip MultiProcessors (C...
The objective of this thesis is to design and implement an FPGA-based softcore processor with hardwa...
Simultaneous multithreading (SMT) allows multiple hardware threads to execute concurrently on a proc...
Existing multiprocessor synchronization mechanisms are relatively heavyweight, due in part to the le...
In this dissertation, we address the problem of performance efficient multithreading execution on he...
A simultaneous multithreading (SMT) processor can issue instructions from several threads every cycl...
In this paper we first outline and discuss the issues of currently accepted computational models for...
In this paper, we present hthreads, a unifying pro-gramming model for specifying application threads...
Hybrid chips containing both CPU's and FPGA components promise the potential of providing a uni...
Abstract 1 This paper discusses the preliminary performance study of hybrid multithreaded execution ...
This thesis proposes, develops, and evaluates hardware and software mechanisms that enhance the effi...
Recently emerging hybrid chips containing both CPU's and FPGA components have the potential to ...
Abstract—This paper introduces hthreads, a unifying program-ming model for specifying application th...
Multithreaded processors are now common in the industry as they offer high performance at a low cost...
Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous ...
This paper evaluates new techniques to improve performance and efficiency of Chip MultiProcessors (C...
The objective of this thesis is to design and implement an FPGA-based softcore processor with hardwa...
Simultaneous multithreading (SMT) allows multiple hardware threads to execute concurrently on a proc...
Existing multiprocessor synchronization mechanisms are relatively heavyweight, due in part to the le...
In this dissertation, we address the problem of performance efficient multithreading execution on he...
A simultaneous multithreading (SMT) processor can issue instructions from several threads every cycl...