Implementation of BIST for an 8-bit SAR ADC on a 0.35um CMOS process

Analog to Digital Converters (ADC) are commonly used in mixed-signal volume circuits. As these circuits become more complex, testing them becomes more difficult especially when they are incorporated in a chip. These circuits should be designed to have the capacity of being tested. This kind of design is called as design for testability (DFT). The use Automated Test Equipment\u27s (ATEs) and Built-in Self Test (BIST) are two ways to test these circuits. Built-in Self Tests are less expensive compared to Automated Test Equipment\u27s. Moreover, BIST enables customers to test ADCs to test faults in the circuit using ordinary test bench equipment\u27s. The purpose of this study is to implement a BIST for an 8-bit Successive Approximation Register (SAR) ADC. The circuit was implemented on a 0.35 um CMOS process. The BIST system has three parts, the Integral Nonlinearity (INL) detector, Differential Nonlinearity (DNL) detector and the output response analyzer (ORA). These circuits are designed to test static parameters of an 8 bit SAR ADC. These parameters are the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL). The INL and DNL detector circuits are composed of logic gates and ramp generators. The group used ORA to show if the circuit has passed the specifications