Design of a 3.3-V rail-to-rail 10-MHz CMOS operational amplifier

A 3.3-Volt rail-to-rail 10 MHz operational amplifier (op-amp) is designed using an industry-grade electronic design automation (EDA) tool, i.e. Electric TM, and simulated using WinSpice. The proposed design makes use of the folded-cascode configuration, which provides the full output swing (rail-to-rail). The design methodology initiates with the following target specifications: Vdd, Vss = ┴3.3 V GBW = 10 MHz Output swing = ┴3.0 V, ┴0.3 V Gain = 74 dB (5000) ICMR = ┴2.0 V Slew rate ≥ 5 V/os Settling time ≤1 os Load (cap.) = 20 pF Phase Margin ≥ 60₀ Min. length = 0.8 om The mask layout is constructed by adopting the MOSIS CMOS technology, which is available in the EDA tool as mocmossub . The generated layout makes use of two metal layers and one polysilicon. The simulations performed both for schematic and mask layout include dc analysis, ac analysis, and transient analysis. The results compare well with the design specifications, particularly the rail-to-rail output swing and unity-gain bandwidth. This study excludes the actual fabrication of the design