FPGA based turbo encoder/decoder using soft output viterbi decoding algorithm

Turbo Codes have gained prominence because of its near channel capacity error correcting capability. Bit streams are encoded by concatenating two parallel convolutional encoders, separated by an interleaver. This results to a code, which when transmitted, achieves a very low (almost zero) bit error rate, when observed at the receiver. A more significant characteristic of this encoding/decoding scheme is how these error stricken codes are recovered by the decoder. By utilizing soft decision decoding and an iterative decoding structure, transmitted sequences are recovered with better efficiency. Given these outstanding features, this study presents how a turbo encoder/decoder is implemented on a Field Programmable Gate Array (FPGA) using the Soft Output Viterbi Decoding Algorithm (SOVA). Several models were synthesized and implemented but only two were chosen, one with the fastest speed and the other with the smallest number of gate utilization. A VHDL model was also created for the 25 and 50 bits frame. The designs performance was verified by comparing it with the results obtained from the MATLAB simulation. The decoder\u27s performance was further validated by measuring and comparing the Bit Error Rate (BER) with published results