Digital Phase-Locked Loop Design for Naval Applications

Most digital control architectures for power system applications require synchronization with the distribution system voltage. Therefore, a phase-locked loop (PLL), implemented in a DSP, is generally among the digital control blocks of the control system. The PLL analyzes the bus voltage and provides power system information for some of the other blocks to do further calculation. Thus, the performance of the PLL has a broad impact on the system performance. Small-scale power systems, such as naval systems, pose a challenging environment for PLL design due to voltage distortion and variation in the fundamental frequency that is large as compared to large terrestrial systems. Our objective is to improve the accuracy of the PLL digital block and hence enhance the digital control system. This research compares two PLL algorithms, as well as the use of a PI controller or lag controller with respect to their steady state and transient performance