Gerçek zamanlı bir sistemin kısmı yeniden yapılandırılabilir FPGA ile gerçekleştirilmesi.

The use of reconfigurable logic has increased in different kinds of applications during the last decades. Compared to other logic solutions reconfigurable logic has advantages such as easy update and lower time to market. The concept of partial reconfiguration in Field Programmable Gate Arrays (FPGAs), which are the most commonly used reconfigurable logic, has recently been introduced by leading FPGA vendors. Partial reconfiguration is a technique that allows reconfiguring a specific part of an FPGA during runtime. This method allows switching between design modules that are not necessary to function at the same time without interrupting the FPGA’s processing of the current task and therefore larger applications may be implemented. This thesis study mostly concentrates on partially reconfigurable architectures. Properties of partially reconfigurable architectures and systems are examined. As a case study, partial reconfiguration has been implemented on an FPGA, which is used as a hardware accelerator in a real-time target detection and tracking system. Using partial reconfiguration, switching between different algorithm components takes place during runtime without interrupting the object-tracking capability. By this approach, FPGA resources are used efficiently and power consumption is reduced.M.S. - Master of Scienc