Görüntüleme sensörleri için düşük güç tüketen CMOS hafıza entegre devresi.

This thesis presents a low power SRAM block implemented in a 0.35 μm CMOS technology for imaging applications to be used inside a digital image processor ASIC (Application Specific Integrated Circuit). The SRAM structure is designed to be fast enough to store all the image data fed by a large format readout circuitry such as VGA (640x512), while requiring low power consumption. The low power consumption is a very critical requirement of such circuit, as the circuit will eventually be used in an embedded platform, which is generally battery operated. The circuitry is implemented with standard six transistor bitcells, write buffers, sense amplifiers, and a timing generator, while each sub-unit is designed very carefully to reduce the overall power consumption of the circuit. All interior signals are created by the timing generator, by asserting two control signals (enable and read/write) and a system clock. Sense amplifiers are selected to be current-type, which helps to improve both area and power consumption without reduced speed performance. The minimum achieved power consumption of the design is 1.28 mW for the read operation and 0.58 mW for the write operation. These numbers are comparable with the state of the art SRAM devices implemented in 14 nm CMOS node, if the capacitance values are scaled for a realistic comparison. This low power SRAM design also aims to be scalable and allows implementing from 4Kbit to 2Mbit storage areas, which correspond to array sizes of 16x256 to 8192x256. This scalable design also utilizes the local word line assertion technique in addition to pulsed synchronous operation to reduce the power consumption of the SRAM further. The local word line assertion also enables multi-port operations with minimal additions to structure, increasing speed performance for imaging applications. In summary, the SRAM presented in this thesis not only satisfies the requirements spatial image processing of VGA image sensors at its maximum frequency for current setup with one-port, but also competes with the state of the art SRAMs in the literature in terms of power consumption.M.S. - Master of Scienc