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Today’s analog modulators and upconverters are inadequate to synthesize and modulate signals with high ‘Spurious Free Dynamic Range’ (SFDR). Thus, the main objective of this thesis is to design and implement a ‘Digital Signal Synthesizer’ (DSS) that is capable of synthesizing signals between 50-100 MHz with 60dB SFDR and to modulate them variable symbol rates and modulation techniques with very high phase/frequency resolution and switching speed while keeping the amplitude modulation occurring during a modulated symbol duration as small as possible. In this thesis, digital words of the desired signals are first synthesized in a ‘Field Programmable Gate Array’ (FPGA) using ‘Direct Digital Synthesizer’ (DDS) fundamentals and then converted to analog signals with a high speed ‘Digital to Analog Converter’ (DAC). In order to attain the analog requirements, the system variables such as DAC analog performance, nonlinearities, sample and hold affects, DDS parameters, system clock, bandwidth requirements of analog filters and how they effect the output performance are studied. FPGA blocks that are capable of modulating and synthesizing desired signals are designed and programmed on a FPGA. Finally, single tone and modulated signals are synthesized with this DSS implementation and measured in order to verify this system’s performance and capabilities.M.S. - Master of Scienc