Automated System Implementation for Digital Signal Processing Based on Circuit Structures for Residue Number Arithmetic

Residue number arithmetic is characterized by a non-weighted number system, where long integer numbers are split into several smaller numbers with restricted numerical range. This allows the computation of long words by several smaller words, which use almost identical circuits in a parallel structure. However, the non-weighted number representation complicates sign detection, the comparison of numbers and the division operation.In this work, circuits are presented to realize sign detection, a comparison of numbers and a division with fixed values. Furthermore, circuits implementing FFT, error correction and number system conversion are shown.The concepts are based on parametrical circuit elements for residue number systems like ABIP, HYBIP and IPSP. The complexity of these three elements is analyzed for a word length in the range of 2 to 7.To carry out an automated system implementation based on circuit structures of residue number arithmetic, a synthesis tool is created. This hardware compiler can be used through a command line or a graphical user interface. The hardware compiler makes complex circuit structures available in parametrical form. Using parameterized modules for the circuit description allows for designs to be easily reused, which allows for more complex circuits. The hardware compiler can simulate and create a VHDL netlist of a circuit. In this manner a link to other synthesis tools is available