PerformanceInvestigation of Access Types to IQC Device

Application-specific integrated circuits (ASIC) are mainly driven by improved power requirements and extensive volume scaling. Ericsson shows that they can downsize their products by using more ASICs, giving easy installation and maintenance. The main drawback with ASIC is that it is fixed at production, compared with software. To improve the flexibility of the chip, CPUs are integrated on-chip and make the available hardware function configurable by the CPUs. The interest in throughput and latency between CPU and hardware components is the increased communication demands and to support better debug capability and backward compatibility. The backward compatibility demanded can be implemented by software instead of hardware. This Master thesis will look inside a subcomponent of an Ericsson chip that controls a radio unit interface, find ways to measure throughput and latency for a packet-based communication between CPUs. The software was developed to parse packet throughput, latency, and loss ratio from simulation and handling multiple runs with different parameters. A test bench was made to run compiled C code for the CPUs in the system. Scripts were made to handle compilation and running simulations where C code with different parameters is integrated. Two different interfaces between CPUs and hardware components were compared. The interfaces were APB/MIRI and AHB with separated read and write channels. The comparison shows that the throughput will increase by 1.1-2.6. Considerable improvement for large packets, while for smaller packets, the overhead is dominating. The maximum write throughput where 400 MB/s for AHB and 161 MB/s for APB/MIRI. Higher throughput can be achieved by using DMA