A new beam synchronous processing architecture with a fixed frequency processing clock: application to transient beam loading compensation in the CERN SPS machine

© 2021 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/New projects being implemented or planned at CERN, such as the LHC Injectors Upgrade (LIU), the High-Luminosity LHC (HL-LHC) or the Future Circular Collider (FCC), motivate the change of several architectural paradigms in the Low Level RF systems (LLRF). In the upgraded Super Proton Synchrotron (SPS) LLRF, the distribution of RF, the revolution frequency, settings and synchronization timings will rely on a deterministic link, the White Rabbit (WR), exploiting a distributed topology. The digital electronics (FPGA) will now use a fixed frequency clock extracted locally in each node from this data stream. The paper presents a new solution for algorithms that treat beam-induced perturbations as they must solve the challenge to tune their processing to the instantaneous revolution frequency, Beam Synchronous Processing (BSP). We use dynamic resampling of uniform sampled data as tuning element between a sweeping spectrum and the static processing implemented with fixed frequency clocks. The paper applies the novel Beam Synchronous Processing method to transient beam loading compensation. It presents a One Turn delay FeedBack (OTFB) for the SPS based on a cascade of two variable ratio resamplers.Peer ReviewedPostprint (author's final draft