Circuit Design Automation for High Speed Interconnects in Advanced Nodes

Design complexity has become is a rising issue in modern Mixed-Signal SOC designs. Especially today's Full-Custom flow lags automation. This thesis tackles this issue in introducing design flows and methods to create expert knowledge-based parametrizable schematics and layouts. In this work, a seamless language bridge between python and SKILL was developed to interface with the commonly used design environment. The skillbridge was opensourced and is widely used. For the schematic a design flow is introduced which guarantees consistency between system-level and implementation. In sizing scripts expert knowledge can be encoded. These scripts are technology agnostic sizing scripts with high reusability. For layout generation, reoccurring layout patterns were identified in industrial design projects and implemented as parametrizable elementary cells. In an initial version, these elementary cells were implemented with a commercial tool the Cadence PCell Designer. Based on lessons learned an own constraint-based layout generation framework was implemented, the XCell framework. The XCell framework offers interfaces to describe tool and technology agnostic generators. With this framework, the elementary cells and many more generators were implemented and successfully used in larger designs. In leaf cells using elementary cells a huge part of the including shapes are generated. When these shapes were sorted by category it was shown that in the local category which includes the DRC critical layers 80% was generated. With this, a significant reduction in design time with reusable layout cells was achieved. This effect is amplified because of all elementary cells being DRC clean and DFM friendly and thus reducing design turnaround cycles