Avires : simulating tiered memory architectures using dynamic binary instrumentation

Increasingly data-centric workloads have challenged and stressed each component of the modern tiered memory architecture. Active research at different levels of granularity is being conducted to accommodate these now normalized workloads. From a feasibility perspective Dynamic Random-Access Memory (DRAM) and its use in memory is one key point of contention for a data-centric application to scale. Various Non-Volatile Memory (NVM) alternatives have emerged as possible solutions to resolve this bottleneck. Of those, at the time of writing, Intel’s DC Persistent Memory (DCPMM) has emerged as the most marketed and commercially viable alternative. Nonetheless, procuring and working with DCPMM Dual In-line Memory Module (DIMM)s has a significantly high barrier to entry. Consequently, progress made to integrate DCPMM into modern tiered memory architectures and application execution is restricted to niche scientific communities. In order to reduce the barrier to entry, we propose AVIRES — A tiered memory architecture simulator that requires no retrofitting of an application with a simple set up. It uses Intel Pin as its Dynamic Binary Instrumentation (DBI) framework to accurately instrument and interpose different tiered memory configurations onto any application’s execution. We have designed, implemented and evaluated AVIRES’ ability to accurately and efficiently simulate impact on real applications. Furthermore, AVIRES can be instrumented at any granularity the developer deems suitable.Computer Science