Design A Low Power And High Throughput Error Detection And Data Correction Architecture By Razor II Method

The proposed error detection and correction circuit designed due to the existing circuits accommodate the worst-case delay. To prevent Error in the system, detect and determine violation to maintain correctness to help on the fly mechanisms. The proposed circuit is to present speculative error detection technique along with an error recovery mechanism. Circuits are wanted to oblige the delay and to get to be deficient in their execution. To enhance the execution, they oblige fly system to forestall, identify and correct errors. In this paper, low power speculative error detection and error recovery architecture are PJAEE, 17 (9) (2020) 4394 to be developed. The main aim of the circuit is to reduce delay, power and area. This paper demonstrates their ability to operate under worst-case accommodation. The proposed error correction and detection circuit give 226nW, propagation delay 1ps, throughput 792MHz.