Convolutional Layer Implementations in High-Level Synthesis for FPGAs

Thesis (Master's)--University of Washington, 2021Field programmable gate arrays (FPGAs) offer a flexible hardware platform on which machine learning algorithms can be efficiently implemented. However, developing these algorithms on FPGAs can be prohibitive due to complex implementation details. We use the HLS4ML (High-Level Synthesis for Machine Learning) framework to translate models trained using traditional machine learning libraries into C++ which can then be translated into FPGAs firmware using High-Level Synthesis (HLS). We propose an alternative approach for convolutional neural networks within the HLS4ML framework. Using the new approach on benchmark convolutional neural network (CNN) models, we show a potential reduction of FPGA critical resource consumption by up to 30% and latency by up to 12%. Lastly, we describe the process in which we integrate the proposed approach in the HLS4ML framework