High-voltage ESD PNP clamp simulation and design

In this work high-voltage Electrostatic discharge (ESD) PNPs are studied through TCAD simulation and device measurement. PNPs for three different voltage classes, 16 V, 65 V, and 100 V, in a 0.5-µm Bipolar CMOS DMOS (BCD) technology are used as the context for the study. The PNPs are varied in choices of topology, layout parameters, and connection configuration to determine how to design an optimal ESD PNP. Analysis of an unexpected two-part on-resistance is discussed. A detailed setup for running TCAD simulations for ESD devices that operate in breakdown, such as the ESD PNP, is also presented. The choice of model selection, differences between 2-D and 3-D simulation, and techniques for proper transmission line pulse (TLP) simulation are discussed. Careful considerations are made to account for the inaccuracies of the simulated doping profiles.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste