Delay Characterization of Cyclone V FPGA

Each new generation of FPGAs features smaller transistor sizes and more densely arranged features. This thesis updates and builds upon the work of Sedcole and Cheung on the 90 nm Cyclone II FPGA by measuring delay variability in a 28 nm Cyclone V FPGA [P. Sedcole and P. Y. K. Cheung. Within-die delay variability in 90nm fpgas and beyond. In 2006 IEEE International Conference on Field Programmable Technology, pages 97–104, 2006. DOI:10.1109/FPT.2006.270300]. Studying the delay variation is impactful for FPGA applications which capitalize on the inherent delays of logic gates. These include time-to-digital converters and physically unclonable functions. In this thesis, I describe the methodology used to characterize the delays of an entire FPGA chip using ring oscillators made from inverter logic gates. In addition, I describe a method to change the routing of an individual inverter and describe the impact this has on timing delay. I found that for ring oscillators contained wholly within a logic cell, LABs and MLABs on the Cyclone V, there were a range of delays. When configured favorably, LABs had an average delay 226 ps and MLABs had an average delay of 237 ps.Moreover, distributions were bimodal. For example, one peak had an average delay of 225ps with a standard deviation of 2 ps and the second peak 237 ps with a standard deviation of 3 ps.No embargoAcademic Major: Physic