Implementing a Time Management Unit for the OR1200 Processor.

This thesis presents a Time Management Unit (TMU) that provides assistance to thescheduler and the interrupt handling of a real-time operation system. The unit providesfunctionality for monitoring task execution time and a mechanism for signalling when atask depletes its resources. This applies to both regular tasks and the handling of sporadicevents. By putting the TMU inside a processor core, it has a more predictable impact onthe overhead related to task switching.The implemented TMU is tested as a stand-alone unit with a hardware testbench,and then integrated into the OpenRISC 1000 based OR1200 processor as special purposeregisters. The behaviour of OR1200 is verified through hardware simulation, usingcompiled software as input. The Or1ksim instruction-set simulator is modified to includethe TMU functionality, which provides a reference point for the behaviour of the alteredprocessor.The real-time operating system FreeRTOS is adapted to utilize the functionality ofthe TMU. Its behaviour is verified through simulation on Or1ksim, simulated hardwareand execution on a Cyclone V FPGA.Analysis of runtime statistics shows that the module is working as expected throughall phases of verification, and that it can increase determinism, reliability and user control.Tests have shown that the TMU is able to recover a faulting task from spin-locks andaid in fail-soft operations for software faults. By placing the TMU inside the processorcore, a fixed overhead of 131 cycles is achieved during a context switch when no cachesare used