Design and Implementation of a Digital Standard Cell Library for 28 nm Technology

A digital standard cell library has been designed and implemented for a 28 nm technology. The library has been designed and optimized for a supply voltage of 300 mV, to be compatible with a standard design flow. Each cell has been characterized with extracted parasitic components. Combinatorial logic gates, including compound logic gates, and sequential cells were implemented with SLVT (Super Low VT) transistors. The library has been used to synthesize a functional RISC-V architecture (PicoRV32). The motivation was to verify the functionality of the standard cell library and obtain quantitative results of the performance of the library. The minimum energy point (at room temperature in the TT-corner) for the CPU was found to be with a supply voltage of 500 mV and a frequency of 20 MHz. By increasing the supply voltage to 600 mV, the CPU supports a 50 MHz clock. The highest simulated frequency was 250 MHz at 1