A Comparative Analysis of Shared Cache Management Techniques for Chip Multiprocessors

In this thesis we present a comparative analysis of shared cache management techniquesfor chip multiprocessors. When sharing an unmanaged cache between multiplecores, destructive interference can reduce the performance of the system as thecores compete over limited cache space. This situation is made worse by streamlikeapplications that exhibit low locality of reference but has high cache demands.Several schemes for dynamically adjusting cache space available to each core hasbeen suggested, and in this work we evaluate 3 such schemes as well as staticpartitioning and conventional LRU.We deploy a well defined simulation methodology to analyze the performance of thecache management techniques. The gem5 simulator is used to simulate the ARMISA, and the SPEC2006 benchmark suite is used to create multi-programmed workloads.The simulator has been extended to support cache management schemes andprovide detailed simulation statistics. We implement UCP, PIPP, PriSM and staticpartitioning, and simulate dual core, quad core and 8 core workloads.Our results show that destructive interference is a real issue in many workloads.Static partitioning can work well in scenarios where applications have similar cachedemands, by creating private areas in the cache for each core. UCP improveson static partitioning by dynamically adjusting the size of each partition duringruntime. PIPP performs decently by trying to maintain a specific cache occupationfor each core without strictly enforcing a partition, but does not quite achieve thedesired occupation and thus its performance suffers. PriSM fails to perform well,as its effort to determine a target cache allocation and maintain it does not worksuccessfully for our workloads