A study of hardware compression of images

In this paper, we will take a closer look at the possibility of compressing images to the JPEG 2000 standard using an FPGA's hardware architecture. This FPGA will be put into a satellite, which is going to orbit the earth in a low earth orbit, so there are considerations to take because of this. The implementation was done in VHDL, and the created modules were simulated using test benches. The simulations were mainly of a created input from the camera. It was run through the module, and the output was analyzed. These simulations point in the direction that the modules work as intended, but there is still further work that needs to be done, in order for the complete system to be implemented in a physical FPGA and launched into space