Portable Stimulus is an upcoming technique for increasing productivity and quality of verification of digital designs. A single test description shall be used to generate tests between multiple abstraction levels and platforms. Questa inFact is a tool that supports a subset of an upcoming standard from Accellera. The thesis consisted of analyzing the current status and future development of Portable Stimulus. This included conducting a proof of concept through inFact. Generated code from a single description was proven to be used in simulation at IP-, sub-system- and SoC-level in UVM testbenches, as well as with C code running on a CPU. Only the stimulus was portable, meaning frameworks for driving the stimulus had to be created. The curr...
When we talk about hardware development, many efforts are made to tape out a bug-free design. The ha...
Simulation-based functional verification is a commonly used technique for hardware verification, wit...
The amount of user interaction is the prime cause of costs in interactive program verification. This...
The thesis is focused on the design and implementation of the portable stimulus verification scenari...
Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (I...
The time used debugging and developing testbenches in FPGA and ASIC/IC projects is around 60% of the...
Simulation-based approaches that require to drive the design under verification (DUV) to specific co...
RESUMEN: El objetivo de este trabajo es explorar una metodología de verificación que permita validar...
The study on verification trends in the semiconductor industry shows that the design complexity is i...
Abstract—Simulation-based verification is still the most fre-quently used technique when complex des...
Analog and mixed-signal circuit designs are more important now than ever, due to the popularity of w...
This paper presents new technology that accelerates system verification. Traditional methods for ver...
We present Ketchum, a tool that was developed to improve the productivity of simulation-based functi...
Nowadays, high-level modelling is becoming more and more popular to build new hardware designs, prov...
The use of virtual prototypes in the semiconductor industry has proven to be a successful approach t...
When we talk about hardware development, many efforts are made to tape out a bug-free design. The ha...
Simulation-based functional verification is a commonly used technique for hardware verification, wit...
The amount of user interaction is the prime cause of costs in interactive program verification. This...
The thesis is focused on the design and implementation of the portable stimulus verification scenari...
Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (I...
The time used debugging and developing testbenches in FPGA and ASIC/IC projects is around 60% of the...
Simulation-based approaches that require to drive the design under verification (DUV) to specific co...
RESUMEN: El objetivo de este trabajo es explorar una metodología de verificación que permita validar...
The study on verification trends in the semiconductor industry shows that the design complexity is i...
Abstract—Simulation-based verification is still the most fre-quently used technique when complex des...
Analog and mixed-signal circuit designs are more important now than ever, due to the popularity of w...
This paper presents new technology that accelerates system verification. Traditional methods for ver...
We present Ketchum, a tool that was developed to improve the productivity of simulation-based functi...
Nowadays, high-level modelling is becoming more and more popular to build new hardware designs, prov...
The use of virtual prototypes in the semiconductor industry has proven to be a successful approach t...
When we talk about hardware development, many efforts are made to tape out a bug-free design. The ha...
Simulation-based functional verification is a commonly used technique for hardware verification, wit...
The amount of user interaction is the prime cause of costs in interactive program verification. This...