Enabling Research on Energy-Efficient System Software Using the SHMAC Infrastructure

The energy efficiency of computer systems is becoming an increasingly important constraint in the design of microprocessors. Energy consumption impacts battery life and electricity bills, while power consumption is important when considering device thermal constraints and cooling costs. These factors have always been important for the embedded, hand-held device and data centre markets. Recently, the breakdown of Dennard scaling has hampered the ability to reduce transistor dimensions while keeping processor power density constant. As high-end processors drive further reduction of transistor dimensions, this breakdown increases the importance of power consumption as a constraint in their design. Heterogeneous processor architectures have the potential of increasing the energy efficiency of computer systems. To research the design and system software control of such systems, the IME faculty at NTNU launched the SHMAC research project. The project ambition is to explore the heterogeneous multicore architecture design space through customization of a generic architecture, which is instantiated on an FPGA to speed up evaluation. However, the current SHMAC infrastructure lacks a method for estimating the energy consumption of a processor chip implementation of the design it embodies. There is also no multi-core operating system available, which hampers research on system software energy efficiency. This dissertation enables research on the energy efficiency of system software using the SHMAC infrastructure by filling these two gaps. First, we extend the existing SHMAC-port of the operating system Barrelfish to support running on multiple cores. Second, we complement the SHMAC infrastructure with an energy efficiency estimation framework. The framework includes a method for creating energy consumption models for hardware components for which only an HDL implementation is available. The efficacy of the method is demonstrated through application on the existing SHMAC hardware components. The average estimation error each cycle from all models combined is 1.1 %. A hardware infrastructure which enhances the SHMAC infrastructure to use these models and report online energy consumption estimates is also included in the framework. The infrastructure enables energy sampling periods of approximately 12 milliseconds, does not impact the FPGA execution speed, and has a total FPGA resource overhead of approximately 18 % for the processor core and 104 % for the router