Performance Oriented Scheduling with Power Constraints

Current technology trends continue to increase the power density of modern processors at an exponential rate. The increasing transistor density has significantly impacted cooling and power requirements and if left unchecked, the power barrier will adversely affect performance gains in the near future. In this work, we investigate the problem of instruction reordering for improving both performance and power requirements. Recently, a new scheduling technique, called Forced Directed Instruction Scheduling, or FDIS, has been proposed in the literature for use in high level synthesis as well as instruction reordering [15, 16, 6]. This thesis extends the FDIS algorithm by adding several features such as control instruction handling, register renaming in order to obtain better performance and power reduction. Experimental results indicate that performance improvements up to 24.62% and power reduction up to 23.98% are obtained on a selected set of benchmark programs