Fault Tolerant Design Verification Through The Use of Laser Fault Injection

Laser Fault Injection (LFI) testing has been demonstrated to be a useful tool in the prediction of single event upset rates in microcircuits. In addition LFI has contributed to the basic understanding of the mechanisms that cause single event upsets. However, very little research has been performed on the viability of LFI as a tool for verifying fault tolerant designs incorporated in ASICs, FPGAs, microprocessors and embedded systems. Current fault tolerant design verification techniques such as simulation and test have several significant limitations that prevent the complete verification of a fault tolerant design. However, LFI possesses spatial, temporal and financial advantages related to its use, which are very beneficial. This thesis presents results of the fault tolerance verification tests that were performed using laser fault injection on a four-bit fault tolerant filter that was implemented in a commercial FPGA