Advancing STTRAM Caches for Runtime Adaptable Energy-Efficient Microarchitectures

Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAM in on-chip caches, due to advantages including non-volatility, low leakage, high integration density, and CMOS compatibility. However, STTRAM's wide adoption in resource-constrained systems is hindered by high write energy and latency. An increasingly popular method to address this challenge involves trading off the non-volatility for reduced write latency and write energy by relaxing the STTRAM's data retention time. To maintain data correctness in a reduced retention time STTRAM, prior work proposed techniques that dynamically refresh the cache blocks after the retention time has elapsed. However, the refresh buffer utilized in the dynamic refresh scheme (DRS) can easily offset the energy efficiency provided by the STTRAM. Our experiments reveal that, to achieve energy-efficient computation, the retention time, which defines how long the cache can retain a cache block without power, may vary for different applications. As such, a major crux of our work is to explore techniques and novel architectures to enable adaptable STTRAM caches for variable runtime application requirements. First, we propose a buffer-free refresh scheme --called mirrorCache-- to eliminate the overheads of the energy-consuming refresh buffer in the DRS. MirrorCache leverages the STTRAM cell's compact feature size and uses an auxiliary segment with the same size as the logical cache size to handle the refresh operations without the overhead of an external refresh buffer. To enable the adaptable retention time STTRAM in level one (L1) data cache, we propose a logically adaptable retention time STTRAM (LARS) cache that allows the retention time to be dynamically specialized to applications' runtime requirements. LARS cache comprises of multiple STTRAM units with different retention times, with only one unit being used at a given time. LARS dynamically determines which STTRAM unit to use during runtime, based on executing applications' needs. For the last-level cache (LLC), we propose a highly adaptable last level STTRAM cache (HALLS) that allows the LLC configurations and retention time to be adapted to applications' runtime execution requirements. We also propose low-overhead runtime tuning algorithms to dynamically determine the best (lowest energy) cache configurations and retention times for executing applications. We propose Prefetch-Aware Retention time Tuning (PART) and Retention time-based Prefetch Control (RPC) to optimize data prefetching in the runtime adaptable retention time STTRAM. Leveraging a new metric, called expired_unused_prefetches---the number of unused prefetches expired by the reduced retention time STTRAM cache---we show that the proper monitoring of the expired_unused_prefetches can accurately determine the best retention time for energy consumption and access latency. For the page walker cache, which is widely used in the memory management unit (MMU) for address translation, we find that a shared PWC can substantially reduce a new kind of misses---and a major source of latency overhead---present in the reduced retention STTRAM: expiration misses. Based on our analysis, we propose NECTAR, which features heterogeneous retention times and a new least-recent used (LRU) retention time-aware replacement policy (LRU-RT) to ensure appropriate runtime block placements to mitigate the latency overhead. We performed detailed experiments to extensively evaluate and quantify the benefits of the work proposed herein. Results reveal that the proposed STTRAM architectures, design approaches, and algorithms can lead to highly energy-efficient and low-overhead memory architectures for emerging resource-constrained computer systems