Electrical Characterisation and Shaping of InAs Nanofins Grown by Selective-Area Epitaxy

Bottom-up growth of III/V semiconductors such as InAs nanowires has seen tremendous research efforts in the last decades, giving rise to a multitude of applications in nanoscience. III/V nanowires are commonly grown from a nanoparticle catalyst. An alternative approach called selective-area-epitaxy uses a patterned amorphous dielectric layer to template growth on a crystalline substrate. It has received significant recent interest as it offers unprecedented shape control and geometries well beyond simple rod-like nanowires. For example, rectangular 2D nanofin structures with typical height and width of order 1 μm and thickness of order 100nm can be grown in large-area arrays with high identicality using a rectangular slot as the template. This thesis is focused on the electrical characterization of these 2D InAs nanofins and their fabrication into more complex nanoscale devices. The first part covers the basic properties of these InAs nanofins: After a characterisation of the growth technique, we measure field-effect transistors with additional Hall contacts at temperatures below 4.2 K. We find carrier densities ∼2×1017 cm−3 and mobilities in the order of 2000 cm2/Vs, values similar to InAs nanowires. Magnetoresistive experiments at T=300 mK reveal weak localisation effects consistent with long coherence lengths and strong spin-orbit coupling. Hall measurements are an important technique to extract carrier densities and mobility in bulk and thin-film semiconductors. However, small-scale Hall devices often have low aspect ratio and contacts that overlap the device channel. This makes them less suited to Hall measurements than traditional Hall bars. We find that the measured Hall voltage can be greatly reduced in such samples, often on the order of 50%. We present finite-element simulations together with experimental data to estimate these reductions and give guidelines on how to design Hall nanodevices that give correct Hall voltages that properly reflect the real intrinsic carrier density. We then develop a wet etchant technique to selectively trim nanofin height as well as shape nanofins laterally. The etch produces low surface roughness features that do not affect transport negatively. We use the etch to fabricate van-der-Pauw multi-terminal devices that can be oriented at any desired angle with respect to the nanofin growth direction. This allows us to observe anisotropic transport along two perpendicular axis within the nanofins. We find the mobility along the〈112〉direction to be ∼3× higher than in the〈111〉crystal orientation. We attribute this anisotropy to the presence of a high density of polytype stacking faults in〈111〉 direction. In the last part of this work, we pair nanowire transistors with soft materials. In §6.1, we characterise the morphology and dielectric properties of ∼20 nm thin parylene-C films that can be used as gate dielectric for nanowire FETs. We show that these films are compatible with chemical passivation treatments on InAs. In §6.2, we use the solid electrolyte Nafion to directly gate n- and p-type nanowires. Together, the n- and p-type transistors form monolithic inverter-circuits that are able to transduce ionic dc and ac signals into electronic ones. This is an important objective for bioelectronic applications such as neural sensing