Efficient Hardware Constructions for Error Detection of Post-Quantum Cryptographic Schemes

Quantum computers are presumed to be able to break nearly all public-key encryption algorithms used today. The National Institute of Standards and Technology (NIST) started the process of soliciting and standardizing one or more quantum computer resistant public-key cryptographic algorithms in late 2017. It is estimated that the current and last phase of the standardization process will last till 2022-2024. Among those candidates, code-based and multivariate-based cryptography are a promising solution for thwarting attacks based on quantum computers. Nevertheless, although code-based and multivariate-based cryptography, e.g., McEliece, Niederreiter, and Luov cryptosystems, have good error correction capabilities, research has shown their hardware architectures are vulnerable to faults due to the complexity and large footprint of the finite field arithmetic architectures used in those architectures. In this dissertation, error detection schemes on various post-quantum cryptosystems that use finite fields are derived, proving the high efficiency and error coverage of such schemes, and the acceptable overhead needed to implement them in deeply-embedded architectures. Moreover, general error detection schemes are derived for finite field arithmetic with polynomial and normal basis, applicable to any classical or post-quantum cryptographic algorithms that use finite field block in their designs