Leakage Power Driven Behavioral Synthesis Of Pipelined ASICs

Traditional approaches for power optimization during high level synthesis, have targetted single-cycle designs where only one input is being processed by the datapath at any given time. Throughput of large single-cycle designs can be improved by means of pipelining. In this work, we present a framework for the high-level synthesis of pipelined datapaths with low leakage power dissipation. We explore the effect of pipelining on the leakage power dissipation of data-flow intensive designs. An algorithm for minimization of leakage power during behavioral pipelining is presented. The transistor level leakage reduction technique employed here is based on Multi-Threshold CMOS (MTCMOS) technology. Pipelined allocation of functional units and registers is performed considering fixed data introduction intervals. Our algorithm uses simulated annealing to perform scheduling, allocation, and binding for obtaining pipelined datapaths that have low leakage dissipation. We have developed fully pre-characterized RT-level leakage libraries for efficient derivation of the cost functions and fast accurate simulations of the synthesized designs. Results show an average leakage power reduction of 38.2% for various benchmarks, and an average area overhead of 6.2% over unoptimized pipelined designs. However when a latency of 1, 2, or 3 is introduced to the schedule length, area optimizations are noticed, which are in the range of 3.89-4.6%. Total leakage reduction however reduces by around 2.8-3.4% for these cases