A Communication-Centric Framework for Post-Silicon System-on-chip Integration Debug

System-on-Chip (SoC) plays an important role in people’s everyday life. These systems are often deployed in critical applications, bugs discovered after their deployment in field can be extremely expensive, resulting in catastrophic loss of company revenues, compromise of personal and national security, and even human life. Post-silicon debug is a critical component of the validation of modern microprocessors and SoC designs. A major challenge in post-silicon debug is the severely limited observability where only a small number of debug interface signals are available to observe a vast space of internal executions of SoC designs. This dissertation addresses the above issues with a post-silicon system-level communication- centric debug framework for SoC designs. This work considers post-silicon integration de- bug of SoC designs, which concerns debugging anomalies in executions of communication protocols among various IPs. It consists of three main concepts: a communication event selection method guided by system-level protocols, an on-chip communication monitoring infrastructure, and an off-chip trace analysis method specifically accounting for the system- level protocols. This framework enhances observability, and enables efficient and accurate reconstruction of the internal executions for SoC designs. This dissertation demonstrates the framework with experiments on a non-trivial multicore SoC prototype and further shows that the proposed framework allows for precise interpretation of the SoC behaviors. More- over, it shows that with only little area overhead, this framework is able to generate rich debugging information. Comprehensive and well defined specifications are the foundation of the above trace analysis framework and many other SoC design activities. However, such specifications are not always in a desired form. Modern SoC specifications can be ambiguous, incomplete or even contain inconsistencies or errors that is common for system-on-chip (SoC) design validation. This dissertation addresses this problem by developing a message flow specification mining approach that automatically extracts sequential patterns from SoC transaction-level traces such that the mined patterns collectively characterize system-level specifications for SoC designs. This approach exploits long short-term memory (LSTM) networks trained with the collected SoC execution traces to capture sequential dependencies among various communication events of those traces. Then, a novel algorithm is developed to efficiently extract sequential patterns on system-level communications from the trained LSTM models. Several trace processing techniques are also proposed to enhance the mining accuracy. We test the proposed approach on simulation traces of a non-trivial multi-core SoC prototype. Initial results demonstrate that the trained neural network model has a high correct rate on extracting the implemented specifications of the SoC model