High Level Synthesis Of An Image Processing Algorithm For Cancer Detection

There is a crucial need for real time detection and diagnosis in digital mammography. To date, most computer aided analysis applications are software driven and normally require long processing times. Digital filtering is often the initial stage in processing mammograms for both automated detection and tissue characterization, which relies on Fourier analysis. In this research the main objective is to lay the groundwork for converting software driven mammography applications to hardware implementations by using Application-Specific Integrated Circuits (ASICs). The long-term goal is to increase processing speed. This research focuses on achieving the main objective by using one specific mammographic image processing application for demonstration purposes. ASICs offer high performance at the price of high development costs and are suitable for real time diagnosis. In this research, we develop a behavioral VHDL model of a specific filtering algorithm. Automatic Design Instantiation System (AUDI)8, a high level synthesis tool is used to automatically synthesize an RTL design from the model. A floating point behavioral component library is developed to support the synthesis of the filtering algorithm. The work shows that the hardware output is identical to the software driven output at when considering eight-bit accuracy and shows only rounding errors at higher storage capacities