3D Stacking: A New Era for the Integrated Circuit

Muhannad Bakir from the Nanotechnology Research Center at the Georgia Institute of Technology, presented a lecture at the Nano@Tech Meeting on March 30, 2010 at 12 noon in room 1116 of the Marcus Nanotechnology Building.Runtime: 60:29 minutesThe information revolution has been the most important economic event of the past century and its most powerful driver has been the silicon integrated circuit (IC). Over the past fifty years, the migration from BJT to CMOS technology combined with transistor scaling has produced exponential benefits in microchip productivity and performance. However, as silicon technology progresses beyond the 45 nm node, the performance of a system-on-a-chip (SoC) has lagged by progressively greater margins to reach the intrinsic limits of each particular generation of technology. A root cause of this lag is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high performance SoC, especially in areas of cooling, off-chip signaling, and power delivery. The need for ever greater off-chip bandwidth will be especially problematic as the number of cores on a microprocessor increases. Revolutionary "silicon ancillary technologies" are needed to address these challenges. Of course, innovation in silicon ancillary technologies will have to be done in parallel with continued innovations at the chip level (improved scaled transistors and interconnects) as well as system architecture among other things. Three-dimensional (3D) system integration can be used to greatly enhance communication between ICs (larger bandwidth, lower latency, and lower energy per bit) as well as enable heterogeneous integration of technologies. However, 3D IC technology also presents challenges. Aside from issues relating to manufacturing, power delivery and cooling of a stack of logic chips presents many challenges. Simply put, it is difficult enough to cool and deliver power to a single processor today. Stacking multiple processors and memory chips, for example, presents formidable challenges that require advanced silicon ancillary technologies. These issues will be discussed in the seminar. This presentation will also discuss the unique opportunities and technologies for 3D heterogeneous integration of CMOS electronics with chemical and bio-sensors