60 GHz CMOS pico-joule/bit OOK receiver design for multi-gigabit per second wireless communications

Component design for a proposed 60 GHz short-range low-power high-data-rate On-Off Keying receiver in a 90 nm CMOS process is presented. The advances in RFCMOS and the commercial need for high data-rate wireless links are discussed as the enabling technology and motivation for research into the development of 60 GHz CMOS radios for wireless personal area networks. System level calculations are presented validating the feasibility of the proposed receiver topology for its target application. The design and simulation results of a 60 GHz low noise amplifier, 60 GHz direct-conversion demodulator (which has generated an invention disclosure), and a baseband amplifier are discussed in detail. Also presented is a discussion of device modeling techniques for millimeter-wave designs. Measured results are presented for the demodulator. Finally, recommendations for future work are presented.M.S.Committee Chair: Laskar, Joy; Committee Member: Cressler, John; Committee Member: Tentzeris, Mano