A GaAs logic family using the feed through evaluation concept is presented. The logic outputs reset to low during the high phase of the clock and evaluate during the low phase of the clock. Resetting to low alleviates the problems of charge-sharing and leakage current associated with other GaAs dynamic logic families. This novel concept is compared with other common GaAs logic circuits in terms of, device count, chip area, delay, clock rate and power consumptio
For the implementation of high-complexity circuits operating at high speed, low-power circuits are e...
In this thesis an improvement to the Gallium Arsenide source coupled FET logic ECL output cell is pr...
The article of record as published may be found at https://doi.org/10.1109/23.488786An introduction ...
In this paper design of fast arithmetic circuits using GaAs based Feed Through Logic (FTL) family [1...
The next generation of super-computers or base band circuits of advanced radio-telecommunication sys...
This paper compares three compatible normally-off classes of digital logic, namely DCFL, SDCFL and S...
A GaAs latch design suitable for dynamic logic families is presented. This novel concept is compared...
Abstract — A modified approach for Feed-Through logic (FTL) is developed in this paper to provide op...
We present in this paper an analytical method for the evaluation of the performances of the BFL (Buf...
This paper presents a survey of low-power digital Gal-lium Arsenide logic applicable to high perform...
Abstract—A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. ...
technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being e...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
Email Print Request Permissions Save to Project A novel GaAs logic family, pseudodynamic latched log...
The advantages and disadvantages of using gallium arsenide (GaAs) dynamic logic in computers and dig...
For the implementation of high-complexity circuits operating at high speed, low-power circuits are e...
In this thesis an improvement to the Gallium Arsenide source coupled FET logic ECL output cell is pr...
The article of record as published may be found at https://doi.org/10.1109/23.488786An introduction ...
In this paper design of fast arithmetic circuits using GaAs based Feed Through Logic (FTL) family [1...
The next generation of super-computers or base band circuits of advanced radio-telecommunication sys...
This paper compares three compatible normally-off classes of digital logic, namely DCFL, SDCFL and S...
A GaAs latch design suitable for dynamic logic families is presented. This novel concept is compared...
Abstract — A modified approach for Feed-Through logic (FTL) is developed in this paper to provide op...
We present in this paper an analytical method for the evaluation of the performances of the BFL (Buf...
This paper presents a survey of low-power digital Gal-lium Arsenide logic applicable to high perform...
Abstract—A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. ...
technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being e...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
Email Print Request Permissions Save to Project A novel GaAs logic family, pseudodynamic latched log...
The advantages and disadvantages of using gallium arsenide (GaAs) dynamic logic in computers and dig...
For the implementation of high-complexity circuits operating at high speed, low-power circuits are e...
In this thesis an improvement to the Gallium Arsenide source coupled FET logic ECL output cell is pr...
The article of record as published may be found at https://doi.org/10.1109/23.488786An introduction ...