Add to ORKGWires have become a major source of bottleneck in current VLSI designs, and wire length prediction is therefore essential to overcome these bottlenecks. Wire length prediction is broadly classified into two types: macroscopic prediction, which is the prediction of wire length distribution, and microscopic prediction, which is the prediction of individual wire lengths. The objective of this thesis is to develop a clear understanding of limitations to both macroscopic and microscopic a priori, post-placement, pre-routing wire length predictions, and thereby develop better wire length prediction models. Investigations carried out to understand the limitations to macroscopic prediction reveal that, in a given design (i) the variability of t...
Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL)...
Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing ...
thesisAs microelectronics continue to scale, the transistor delay decreases while the wire delay re...
In this paper, the classic wire-length estimation problem is addressed and a new statistical wire-le...
We address the classic wire-length estimation problem and propose a new statistical wire-length esti...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
Concern about the performance of wires in scaled technologies has led to research exploring other co...
A priori wirelength estimation is concerned with predicting various wirelength characteristics befor...
ABSTRACT – We present a novel technique for estimating individual wire lengths in a given standardce...
Interconnect scaling to deep submicron processes pre-sents many challenges to today’s CAD flows. A r...
Abstract—Based on Rent’s Rule, a well-established empirical relationship, a rigorous derivation of a...
Wirelength estimation techniques typically contain a site density function that enumerates all possi...
Interconnect prediction is very important for early feasibility studies in modern design flows. Most...
Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing o...
In this paper, a simple power-distribution electrothermal model including the interconnect self-heat...
Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL)...
Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing ...
thesisAs microelectronics continue to scale, the transistor delay decreases while the wire delay re...
In this paper, the classic wire-length estimation problem is addressed and a new statistical wire-le...
We address the classic wire-length estimation problem and propose a new statistical wire-length esti...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
Concern about the performance of wires in scaled technologies has led to research exploring other co...
A priori wirelength estimation is concerned with predicting various wirelength characteristics befor...
ABSTRACT – We present a novel technique for estimating individual wire lengths in a given standardce...
Interconnect scaling to deep submicron processes pre-sents many challenges to today’s CAD flows. A r...
Abstract—Based on Rent’s Rule, a well-established empirical relationship, a rigorous derivation of a...
Wirelength estimation techniques typically contain a site density function that enumerates all possi...
Interconnect prediction is very important for early feasibility studies in modern design flows. Most...
Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing o...
In this paper, a simple power-distribution electrothermal model including the interconnect self-heat...
Hierarchical design spans the complete framework of a design flow from Register Transfer Level (RTL)...
Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing ...
thesisAs microelectronics continue to scale, the transistor delay decreases while the wire delay re...