The actor model which is a concurrent computing model that seems to be well suited to the massively parallel architecture execution model. We investigate its adequacy to a massively parallel fine grain machine ; we derive the basic mechanisms to be integrated at the routing unit level of this machine. For dynamic programming models of this kind, it is necessary to establish a stra= tegy for dynamic process allocation. We propose and evaluate an original approach= for dynamic process allocation in a massively parallel architecture. In the case of a fine grain machine as ours, it is essential that= such a function implies a minimum overhead in terms of communications. We introduce= an integrated hardware function that takes in charge the sear...
Since 2005, chip manufacturers have stopped raising processor frequencies, which had been the primar...
Le développement des systèmes massivement parallèles de type manycores permet d'obtenir une très gra...
TLM-DT modeling techniques, based on the highest abstraction level of the SystemC hardware descripti...
The actor model which is a concurrent computing model that seems to be well suited to the massively ...
This thesis is a contribution to the study of dynamic investment process on multiprocessor machines ...
This paper presents a new parallel processing scheme called DYNAMIC-JOIN for OPS5-like production sy...
En réponse à la demande croissante de performance par une grande variété d’applications (exemples : ...
Dans cette thèse, nous étudions l’algorithmique parallèle à grande échelle de quelques problèmes en ...
The aim of this thesis is to model and to evaluate load transferring algorithms in parallel and/or d...
La simulation est une étape primordiale dans l'évolution des systèmes en réseaux. L’évolutivité et l...
A foundational model of concurrency is developed in this thesis. We examine issues in the design o...
A foundational model of concurrency is developed in this thesis. We examine issues in the design of ...
L'IMPLANTATION OPTIMISEE D'ALGORITHMES REACTIFS SUR DES ARCHITECTURES PARALLELES, EST UN PROBLEME CO...
The work presented here is part of a general project within the LICM laboratory, concerning the arch...
Actuellement, la majorité des architectures de processeurs sont fondées sur une mémoire partagée ave...
Since 2005, chip manufacturers have stopped raising processor frequencies, which had been the primar...
Le développement des systèmes massivement parallèles de type manycores permet d'obtenir une très gra...
TLM-DT modeling techniques, based on the highest abstraction level of the SystemC hardware descripti...
The actor model which is a concurrent computing model that seems to be well suited to the massively ...
This thesis is a contribution to the study of dynamic investment process on multiprocessor machines ...
This paper presents a new parallel processing scheme called DYNAMIC-JOIN for OPS5-like production sy...
En réponse à la demande croissante de performance par une grande variété d’applications (exemples : ...
Dans cette thèse, nous étudions l’algorithmique parallèle à grande échelle de quelques problèmes en ...
The aim of this thesis is to model and to evaluate load transferring algorithms in parallel and/or d...
La simulation est une étape primordiale dans l'évolution des systèmes en réseaux. L’évolutivité et l...
A foundational model of concurrency is developed in this thesis. We examine issues in the design o...
A foundational model of concurrency is developed in this thesis. We examine issues in the design of ...
L'IMPLANTATION OPTIMISEE D'ALGORITHMES REACTIFS SUR DES ARCHITECTURES PARALLELES, EST UN PROBLEME CO...
The work presented here is part of a general project within the LICM laboratory, concerning the arch...
Actuellement, la majorité des architectures de processeurs sont fondées sur une mémoire partagée ave...
Since 2005, chip manufacturers have stopped raising processor frequencies, which had been the primar...
Le développement des systèmes massivement parallèles de type manycores permet d'obtenir une très gra...
TLM-DT modeling techniques, based on the highest abstraction level of the SystemC hardware descripti...