With the evolution of the complexity and performances of digital circuits, the occurrence of failures which can not be modeled by simple stuck-at faults becomes important and even preponderant. These effects are generally not taken into account by classical diagnosis methods. The purpose of this thesis is to develop a diagnosis method targeting an enlarged set of fault models. In this manuscript, the developed diagnosis method is presented in a progressive way. First, the considered fault models are analyzed in order to show the sensitization conditions. The second part is dedicated to the whole presentation of the proposed diagnosis method. This method mainly uses an "effect-cause" approach based on critical path tracing. The third part pr...
ISBN 2-84813-044-XThe probability of transient faults increases with the evolution of technologies. ...
Automatic diagnosis of design errors is an important problem in digital circuits CAD. Although autom...
As the memory cell design rule is scaled down and the memory array density is increased, EEPROM non ...
Avec l'évolution de la complexité et des performances des circuits intégrés, l'occurrence de défaill...
Les dernières technologies comme la 65nm, 45nm et la nouvelle technologie 32nm qui sera disponible à...
Les dernières technologies comme la 65nm, 45nm et la nouvelle technologie 32nm qui sera disponible à...
Fault diagnosis of ICs has grown into a special field of interest in semiconductor industry. At the ...
Le diagnostic de fautes est essentiel pour atteindre l'objectif de temps avant mise sur le marché (t...
Due to integration density evolution and the high complexity of manufacturing process for integrated...
La croissance rapide dans le domaine des semi-conducteurs fait que les circuits digitaux deviennent ...
This paper presents a unified diagnosis method targeting most of the fault models used in practice t...
ISBN : 2-84813-092-XThe probability of transient faults increases with the evolution of the technolo...
ISBN: 0792377311We describe a new method for design error diagnosis in digital circuits that does no...
Nowadays, embedded memories occupy a large part of the System-on-Chip (SoC) silicon area. Consequent...
Le diagnostic des systèmes automatiques consiste à remonter des symptômes perçus vers les causes. Le...
ISBN 2-84813-044-XThe probability of transient faults increases with the evolution of technologies. ...
Automatic diagnosis of design errors is an important problem in digital circuits CAD. Although autom...
As the memory cell design rule is scaled down and the memory array density is increased, EEPROM non ...
Avec l'évolution de la complexité et des performances des circuits intégrés, l'occurrence de défaill...
Les dernières technologies comme la 65nm, 45nm et la nouvelle technologie 32nm qui sera disponible à...
Les dernières technologies comme la 65nm, 45nm et la nouvelle technologie 32nm qui sera disponible à...
Fault diagnosis of ICs has grown into a special field of interest in semiconductor industry. At the ...
Le diagnostic de fautes est essentiel pour atteindre l'objectif de temps avant mise sur le marché (t...
Due to integration density evolution and the high complexity of manufacturing process for integrated...
La croissance rapide dans le domaine des semi-conducteurs fait que les circuits digitaux deviennent ...
This paper presents a unified diagnosis method targeting most of the fault models used in practice t...
ISBN : 2-84813-092-XThe probability of transient faults increases with the evolution of the technolo...
ISBN: 0792377311We describe a new method for design error diagnosis in digital circuits that does no...
Nowadays, embedded memories occupy a large part of the System-on-Chip (SoC) silicon area. Consequent...
Le diagnostic des systèmes automatiques consiste à remonter des symptômes perçus vers les causes. Le...
ISBN 2-84813-044-XThe probability of transient faults increases with the evolution of technologies. ...
Automatic diagnosis of design errors is an important problem in digital circuits CAD. Although autom...
As the memory cell design rule is scaled down and the memory array density is increased, EEPROM non ...