The evolution of the microelectronic technology leads to a transistors integration density always stronger. The Damascene copper interconnections structures follow this tendency and must be controlled in terms of manufacturing, performance and robustness, these different aspects being intimately related to the residual stresses and resistivity. This thesis aims to understand the mechanisms of the residual stresses generation and identify the different contributions to the resistivity of these objects as a function of annealing conditions and dimensions (from about a hundred of nm to several µm). In order to do this, the respective effects of the microstructure and dimensions of electroplated copper films and lines were separated on the basi...
The continued scaling of Cu low k technology is facing serious challenges imposed by basic limits fr...
Copper interconnects in microelectronics have long been plagued with thermo-mechanical reliability i...
With continued shrinking of CMOS technology to reduce the gate delay times, an increase in the resis...
L’évolution de la technologie microélectronique conduit à une densité d’intégration toujours plus fo...
L évolution de la technologie microélectronique conduit à une densité d intégration toujours plus fo...
The resistivity and reliability of copper in interconnections of the integrated circuits for the 90 ...
In integrated circuits, interconnects have a role more and more important since the number component...
International audienceIn this article, we focus on the possible influence of interconnect Cu microst...
International audienceMechanical stress in damascene copper/low-k interconnects has been studied by ...
Recently Al was replaced by Cu as an interconnecting material. The primary objective of the present ...
Copper films of different thicknesses between 0.2 and 2 microns were electroplated on adhesion-promo...
Electromigration is one of the major cause of copper interconnect degradation which limits reliabili...
De part les hautes densités d intégration atteintes dans les circuits intégrés avancés, les intercon...
In modern microelectronics, material related issues emerge as new technologies are introduced. The p...
textThe scaling required to accommodate faster chip performance in microelectronic devices has neces...
The continued scaling of Cu low k technology is facing serious challenges imposed by basic limits fr...
Copper interconnects in microelectronics have long been plagued with thermo-mechanical reliability i...
With continued shrinking of CMOS technology to reduce the gate delay times, an increase in the resis...
L’évolution de la technologie microélectronique conduit à une densité d’intégration toujours plus fo...
L évolution de la technologie microélectronique conduit à une densité d intégration toujours plus fo...
The resistivity and reliability of copper in interconnections of the integrated circuits for the 90 ...
In integrated circuits, interconnects have a role more and more important since the number component...
International audienceIn this article, we focus on the possible influence of interconnect Cu microst...
International audienceMechanical stress in damascene copper/low-k interconnects has been studied by ...
Recently Al was replaced by Cu as an interconnecting material. The primary objective of the present ...
Copper films of different thicknesses between 0.2 and 2 microns were electroplated on adhesion-promo...
Electromigration is one of the major cause of copper interconnect degradation which limits reliabili...
De part les hautes densités d intégration atteintes dans les circuits intégrés avancés, les intercon...
In modern microelectronics, material related issues emerge as new technologies are introduced. The p...
textThe scaling required to accommodate faster chip performance in microelectronic devices has neces...
The continued scaling of Cu low k technology is facing serious challenges imposed by basic limits fr...
Copper interconnects in microelectronics have long been plagued with thermo-mechanical reliability i...
With continued shrinking of CMOS technology to reduce the gate delay times, an increase in the resis...