The use of floating point arithmetic in scientific computations is a source of problems of precision. Since all real numbers cannot represented in floating-point format, some will have to be approximated. The discrete stochastic arithmetic permits to control and estimate rounding errors. The software implementation of this arithmetic suffers from computation bottlenecks. The aim of this thesis is to propose a hardware architecture to reduce this cost. First we implemented in hardware the specific functionalities of discrete stochastic arithmetic which are the random rounding mode, the computation of the number of significant bits, the detection of informatical zeroes and the control of the operations of comparison. Second, since the discret...